1. Field of the Invention
This invention relates generally to the field of analog circuit design. More particularly, the invention relates to an apparatus and method for ensuring the proper operation of a delay locked loop, even in the presence of missing clock edges.
2. Description of the Related Art
For years, delay locked loops ("DLLs") have been used extensively in the field of analog circuit design. More recently, with the increasingly stringent timing requirements of high performance computing and communications systems today, DLLs are frequently being employed in digital circuit designs (e.g., computer motherboards, high performance multimedia boards, intelligent wireless devices . . . etc).
The design goal of a DLL is to generate a clock which is delayed by a specified number of clock periods with respect to the input clock. For this reason, DLLs are commonly used in applications which require clock-skew elimination, clock/data recovery and multi-phase clock generation.
FIG. 1 illustrates a block diagram of a traditional DLL circuit. The input clock 105, passes through a voltage controlled delay line ("VCDL") 110 which generates a delayed version (CLK.sub.out) 120 of the input clock 105. The delay in the VCDL 110 must be set precisely to some multiple of the input clock 105 period (e.g., 2.times., 3.times., etc., depending on the application). The delay through the VCDL 110 is controlled by a control voltage 115. The higher the control voltage 115, the shorter the delay between the input and output clocks.
The control voltage 115 (and, therefore, the amount of delay in the VCDL 110) is modified by a feedback loop which consists of a phase detector 125, a charge pump 130 and a capacitor 135. The phase detector 125 detects the actual time delay (i.e., the phase difference) between the input clock 105 and the output clock 120 and, in response, causes the charge pump 130 to generate either a positive or a negative current pulse. A positive pulse charges the capacitor 135, increasing the control voltage 115, and a negative pulse discharges the capacitor 135, decreasing the control voltage 115. Accordingly, if the delay of the output clock 120 is too high, the charge pump 130 provides a positive current pulse (increasing the control voltage 115), and if the delay is too short, the charge pump 130 provides a negative current pulse (decreasing the control voltage). The feedback loop will settle when the delayed clock 120 is at the desired phase multiple of the input clock 105 (i.e. the delay is 1, 2, 3, etc. input clock periods).
While DLLs have the advantage of lower order transfer functions (hence having high stability with relatively low jitter), it is important that DLLs be started in a known state to ensure that the delayed clock is locked to exactly one reference clock period (or `n` clock periods, depending on the application). A missing clock edge can cause the phase detector 125 to force the DLL to lock to an incorrect delay which is a multiple of this period (or "zero" delay). In this case, the delayed clock edges may appear to be aligned with the reference clock edges when, in reality, they are improperly skewed by one or more clock periods.